What happens when the AI arms race outgrows the bandwidth of traditional infrastructure? That's the question that led me to a fascinating conversation with members of the UALink Consortium during the IT Press Tour in California. And what I found wasn't just another spec sheet or protocol update. It was the early blueprint for how hyperscale AI might scale.
Let's be honest, we've heard plenty about GPUs, TPUs, and massive AI clusters. However, the fabric that determines how fast, efficiently, and securely data can move between accelerators is often overlooked. UALink is challenging that mindset by building an open, scalable alternative explicitly designed for AI's next chapter.
Why Interconnects Matter More Than Ever
The rise of foundation models, agentic AI, and real-time inference has created a significant bottleneck in communication between accelerators. Moving data within a single node is no longer enough.
AI workloads now require massive scale-up pods connected to hundreds or even thousands of GPUs across multiple racks. Ethernet, despite its ubiquity, wasn't designed for this. PCIe, despite its low latency, struggles with scalability.
This is where UALink steps in. Built by a consortium that includes AMD, Intel, Meta, Microsoft, Google, Cisco, and AWS, UALink aims to combine the raw throughput of Ethernet with the latency characteristics of PCIe, while slashing power usage and complexity in the process. It is not a replacement for Ethernet, but a targeted enhancement for the parts of the AI stack where latency and bandwidth are deal-breakers.
A New Fabric for a New Era
During the presentation, Kurtis Bowman (Chair of the UALink Consortium and AMD's VP of Server Product Marketing) laid out the case for why UALink isn't just technically necessary but strategically overdue.
The 1.0 specification enables up to 800 Gbps per port and scales to 1,024 accelerators per pod. This means that within a tightly knit AI workload, such as a training run across a sovereign LLM, GPUs can communicate directly using memory semantics, not just messaging APIs. Think load/store and atomic operations across accelerators, without needing to route through host memory.
This isn't just a performance boost. It simplifies software. Reduces power. Shrinks die area. And most importantly, it avoids the cost and complexity that often come with proprietary fabrics.
What Makes UALink Different
Rather than reinvent the wheel, UALink cleverly builds on the proven success of Ethernet's ecosystem. That includes reusing existing cables, connectors, retimers, and even management tools. But the protocol stack is stripped down and re-optimized for AI. That means fixed FLIT sizes, compressed request headers, and an emphasis on simplicity and efficiency.
The result is a switch design that's leaner, faster, and cheaper. A pod architecture that can support Virtual Pods, isolating errors and improving reliability. And a security layer, UALinkSec, that supports encrypted communication between accelerators, even in confidential computing environments. From a technical standpoint, this isn't incremental. It's foundational.
The Industry's Quiet Pivot to Open Standards
What impressed me most was the commitment to openness. The UALink Consortium isn't positioning this as an exclusive club or a vendor lock-in tool. The spec is open. The protocol is vendor-neutral. And the invitation to contribute is still open, with more than 70 members already on board.
That matters. Because if we're serious about sustainable, interoperable AI infrastructure, it cannot be built on closed, proprietary pipelines. Especially not when the pace of innovation in AI means you need every tool in the ecosystem to work together.
Final Thought
As I left the meeting, I kept thinking: AI isn't just a computational problem. It's a systems problem. And the way we wire these systems together will shape what's possible in the decade ahead.
UALink may not be a household name yet. Still, if this consortium gets it right, it could quietly become the backbone of hyperscale AI, not with headlines or hype, but by solving one of the most complex infrastructure problems with elegant, open engineering.
Should we start paying more attention to what connects our accelerators, not just the chips themselves? I'd love to hear your thoughts.
I will be speaking with the team at UALink on the Tech Talks Daily Podcast in the next few weeks. If you have any questions you would like me to ask, please let me know.